Integrated circuits, including computer chips, are manufactured by building up layers of circuits on the front side of silicon or other semiconductor wafers. An extremely high degree of wafer flatness and layer flatness is required during the manufacturing process. Chemical mechanical planarization (CMP) is a process used during device manufacturing to polish wafers and the layers built-up on wafers to the necessary degree of flatness.
Chemical mechanical planarization is a process involving the polishing of a wafer with a polishing pad combined with the chemical and physical action of a slurry pumped onto the pad. The wafer is held by a wafer carrier, with the backside of the wafer facing the wafer carrier and the front side (device side) of the wafer facing a polishing pad. A retaining ring extends downwardly from the outer portion of the wafer carrier and surrounds the outer edge of the wafer during polishing. The retaining ring thus prevents the wafer from being pulled or pushed away from the carrier during polishing. The retaining ring also affects how the pad contacts the edge of the wafer. In particular, the bottom surface of the retaining ring is kept even with the front surface of the wafer, thereby ensuring that the polishing pad evenly wears the wafer.
A polishing pad used to polish the wafer is held on a platen, which is usually disposed beneath the wafer carrier. Both the wafer carrier and the platen are rotated so that the polishing pad polishes the front side of the wafer. A slurry of selected chemicals and abrasives is pumped onto the pad to affect the desired type and amount of polishing.
By using this process, a thin layer of material is removed from the front side of the wafer or wafer layer. The layer may be a layer of oxide grown or deposited on the wafer or a layer of metal deposited on the wafer. The removal of the thin layer of material is accomplished to reduce surface variations on the wafer. Thus, the wafer and layers built-up on the wafer are very flat and/or uniform after the process is complete. Typically, more layers are added and the chemical mechanical planarization process repeated in subsequent polishing cycles. When all layers have been added and all cycles have been completed, a plurality of integrated circuit chips are built-up on the front side of the wafer.
A problem encountered during polishing is that a different amount of material is removed from the front side of the wafer near the outer edge of the wafer relative to the central portion of the front side of the wafer. (For the sake of simplicity, the portion of the front side of the wafer near the outer edge of the wafer shall be referred to as the edge of the wafer.) This type of wear is sometimes referred-to as the “edge effect.” One way to handle the problem of the edge effect is to leave the edge of the wafer free of built-up devices. However, this method wastes available space on a wafer and is thus an inefficient method of manufacturing. Thus, improved methods and device are needed to reduce the edge effect and to polish wafers uniformly across the entire surface of a wafer.